Integral mixer and oscillator device

ABSTRACT

A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filer network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No. 10/254,332, filed Sep. 25, 2002 and entitled “Integral Mixer and Oscillator Device,” which claimed priority from U.S. Provisional Application Ser. No. 60/328,411, filed Oct. 12, 2001. The entire specifications of these applications, including the drawing figures, are hereby incorporated into the present application by reference.

BACKGROUND

1. Technical Field

This invention relates generally to the fields of Radio Frequency (RF) mixers and oscillators. More particularly, the invention relates to the integration of mixers and oscillators.

2. Description of the Related Art

Oscillators are used to provide a time varying signal in electronic circuits and are well known to those of skill in the art. FIG. 1 illustrates a typical oscillator known in the art. This oscillator is a negative resistance cell 10. A simple differential pair of transistors Q₁ and Q₂ is shown. The emitters of both devices, e₁ and e₂, are connected, either by a short circuit or other connection, thereby defining a common node n₁. Current source I₁ is connected to the common node n₁. In the most basic case the current source I₁ is a direct current (DC) source, as shown.

CN₁ and CN₂ are symmetric coupling networks, which may consist of short circuits, capacitors, transistors, or other circuit elements alone or in combination. For instance, if CN₁ is an RC network, then CN₂ is preferably an identical RC network. Connecting coupling networks CN₁ between b₁ and c₂, and CN₂ between b₂ and c₁, as shown, generates a differential negative resistance between nodes a and a′, or between any other two symmetric differential points in circuit 10 such as between bases b₁ and b₂, or even between corresponding differential points inside networks CN₁ and CN₂. For instance, if CN₁ has a first resistor, then by symmetry CN₂ preferably has a corresponding second resistor, and a differential negative resistance can be found between one node of the first resistor in CN₁ and another corresponding symmetric nod of the second resistor in CN₂.

If a connection is made between a and a′, such that the connection provides an impedance with a real component greater than or equal to the real value of the negative resistance, circuit 10 will oscillate. The frequency of the oscillation will be determined by the impedance connected between a and a′. The oscillating output signal is produced over the connection between a and a′. In frequency conversion applications, the desired output signal is typically used as a signal source for another circuit.

FIG. 2 illustrates a single balanced mixer 20, which is known in the art. A differential pair of transistors Q₃ and Q₄ is shown. The emitters e₃ and e₄ are connected in the same manner as those in FIG. 1, thereby defining common node n₇. A current source I₂ is connected to the common node n₇. In this instance, the current source I₂ has both a DC component (I_(dc)) and a frequency component (I_(RF)) at frequency f_(RF).

Unlike the negative resistance cell 10, there is no cross coupling. Instead a frequency source, S₁, providing an LO (Local Oscillator) signal at frequency f_(LO), is connected between bases b₃ and b₄. This LO signal varies the amount of current flowing through each transistor Q₃ and Q₄ such that the differential component of the current, provided by collectors c₃ and c₄ when a load is connected between nodes d and d′, has frequency components at DC, f_(LO), and f_(LO)±f_(RF). In frequency conversion applications, the desired output signal is typically one of the frequency translated components of I_(RF), at either f_(LO)−f_(RF) (down-converter) or f_(LO)+f_(RF) (up-converter).

Although known oscillators and mixers can be combined, as they are in frequency conversion applications, the result is often far from ideal. In most applications, the mixer and oscillator are separate circuits. This results in an increase in both component area and power consumption, which results in a device that is costly to manufacture and operate. Furthermore, the physical distance between oscillator and mixer circuits often results in leakage of the local oscillator signal to other circuits, which is disadvantageous, as one of skill in the art will appreciate.

It is, therefore, desirable to provide a device that provides the functionality of both an oscillator and a mixer, which decreases the required power and area required to implement. Additionally, it would be desirable to provide a device that reduces the leakage of the oscillator signal to other circuits.

SUMMARY

It is an object of the present invention to obviate or mitigate at least one disadvantage of previous mixer-oscillator arrangements. It is a further object of the present invention to provide a device with integral oscillation and mixing functionality.

In a first aspect, the present invention provides a device, which has a plurality of nodes, for generating both an oscillating output signal and a mixed output signal based on a time varying input signal. The mixed output signal represents a translation of the input signal by the oscillating output signal. The device has a differential pair of transistors for receiving the time varying input signals and for generating a differential pair output signal having a time varying input component and other components, and a first filter network that is connected to the differential pair for receiving the varying input signal component from the differential pair. The first filter network selectively generates a negative resistance at the desired oscillating frequency across two nodes connected to the first filter network, and selectively provides the oscillating output signal by providing an impedance across the two nodes. Once the oscillating signal is established, the outputs of the differential pair contain frequency components of both the oscillating signal and signal components caused by the mixing of the input signal with the oscillating signal in the differential pair. Connected to the first filter network and the differential pair is a second filter network. The second filter network receives the oscillating output signal, and receives the other signal components, generates, and selectively passes the mixed output signal.

In a further embodiment, the time varying input signal has both time varying and constant components. In other embodiments, the negative resistance is generated across nodes connected to the collectors of the differential pair, and the magnitude of the resistance is proportional to the magnitude and frequency of the time varying input signal. Alternate embodiments include means for generating the mixed output signal by translating the oscillating output signal by the frequency of the time varying signal, this translation can be both positive and negative.

In a further embodiment of the present invention, the device has a second differential pair of transistors for receiving a second time varying input. The second differential pair provides this input to the first and second filter networks. The first filter network generates a negative resistance across two pairs of nodes in parallel with each other and the second filter network cancels output signals that have the frequency of the oscillating output signal. In alternate embodiments the time varying signals are out of phase with each other, and the overall negative resistance is substantially constant. In various embodiments, the first and second networks can be either high or low pass filters, either of which can be tuneable. In yet another embodiment, there is an input circuit that generates the out of phase time varying input signals using a differential pair of transistors connected to a constant signal, and a time varying signal and a biasing signal.

In a further aspect, the present invention provides a device for receiving a time varying input signal and for generating both an oscillating output signal, and a mixed output signal, the mixed output signal representing a translation of the oscillating output signal, the device having a plurality of nodes. The device has first and second differential pairs of transistors, each pair receiving a time varying input signal. A first filter network is operatively connected to the differential pairs and receives from them the two time varying input signals. These input signals are used to generate a negative resistance across two pairs of nodes connected in parallel to the first filter network. The first filter network selectively provides the oscillating output signal by providing an impedance across the parallel negative resistance. A second filter network is operatively connected to the two pairs of nodes, for receiving the oscillating output signal, and is also operatively connected to the differential pairs for receiving the time varying signals. The second filter network selectively passes the mixed output signal. In alternate embodiments of the present invention the time varying input signals are out of phase, the first filter network is a tuneable high pass filter, and the second filter network is a low pass filter.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way of example only, with reference to the attached figures, wherein:

FIG. 1 is a schematic diagram showing an oscillator of the prior art;

FIG. 2 is a schematic diagram showing a mixer of the prior art;

FIG. 3 is a schematic diagram showing an exemplary single balanced mixillator, according to an embodiment of the claimed invention;

FIG. 4 is a schematic diagram showing an exemplary dual balanced mixillator according to a further embodiment of the claimed invention;

FIG. 5 is a schematic diagram showing an exemplary HPF (High Pass Filter) suitable for use as a filter network in a frequency down conversion application of the mixillator of FIG. 4;

FIG. 6 is a schematic diagram showing an exemplary LPF (Low Pass Filter) suitable for use as a filter network in a frequency down conversion application of the mixillator of FIG. 4; and

FIG. 7 is a schematic diagram showing an exemplary input stage suitable for use as the two current sources for the dual balanced mixillator of FIG. 4.

Same reference numerals are used in different figures to denote similar elements.

DETAILED DESCRIPTION OF THE DRAWINGS

Generally, the present invention provides a system for generating a mixed output signal and an oscillating output signal based on a time varying input signal. The mixed output signal is the oscillating signal translated by a time varying factor of the input signal. A dual balanced embodiment of the device that makes use of a differential pair to provide out of phase input signals is also disclosed. The device provides the functionality of both an oscillator and a mixer, which decreases the required power and area required to implement. Additionally it reduces the leakage of the oscillator signal to other circuits.

FIG. 3 illustrates an embodiment of the present invention. The device 30 comprises a circuit with both oscillator and mixer functionality. Device 30, which is preferably referred to as a “mixillator”, includes a simple differential pair of transistors Q₅ and Q₆, as well as two filter networks FN₁ and FN₂, for generating an oscillating output signal, LO, and mixing LO with an external input signal to produce an output mixed signal

As with the separate oscillator 10 and mixer 20 of FIGS. 1 and 2, circuit 30 has a differential pair of transistors, Q₅ and Q₆, connected at the emitters e₅ and e₆ thereby defining common node n₁₁. A current source I₃, which has both DC (I_(dc)) and time varying or RF (I_(RF)) components is connected to the common node n₁₁. Connected to the collectors c₅ and c₆ of Q₅ and Q₆, are two filter networks, FN₁ and FN₂. FN₁ is further connected to bases b₅ and b₆ of Q₅ and Q₆. FN₂ provides a differential output between nodes f and f′ which corresponds to the output of a conventional mixer driven by a conventional oscillator.

To understand the operation of device 30, consider the circuit of FIG. 3 in the absence of FN₂, where I_(RF)=O. Under these conditions, FN₁ connects b₅ and b₆ to c₅ and c₆. Thus FN₁ is analogous to a combination of CN₁ and CN₂ of FIG. 1, which connect b₁ to c₂ and c₁ to b₂ respectively. In this configuration, it is apparent that FN₁ must provide a negative resistance across two nodes connected to FN₁. These nodes can be internal to FN₁, as were the nodes in the prior art example, or external nodes such as n₁₂ and n₁₃ or n₁₄ and n₁₅. In the presently illustrated embodiment, FN₁ provides a negative resistance across nodes n₁₄ and n₁₅. A negative resistance must also be seen at n₁₂ and n₁₃, although it has a different value.

To further understand FN₁, consider the circuit of FIG. 3 in the absence of FN₂ and where I_(RF) is non-zero. The single balanced mixer 20 of FIG. 2, provides current at the output d/d′ of the circuit 20, the current having components at DC, f_(LO), and f_(LO)±f_(RF). Therefore, in the presence of an RF component, it is no longer sufficient for FN₁ to simply generate a negative resistance at the LO frequency, as was done in the prior art. In the embodiment of FIG. 3, FN₁ still generates a negative resistance at the desired oscillator frequency f_(LO), but FN₁ preferably does not generate a negative resistance at the desired mixer output frequencies, f_(LO)−f_(RF) or f_(LO)+f_(RF). FN₁ provides negative resistance, and thus an oscillating output, between b₅ and b₆ at f_(LO), but does not provide an oscillating output at the mixer output frequencies of f_(LO)−f_(RF) or f_(LO)+f_(RF). This frequency selectivity in FN₁ provides oscillator functionality in the presence of an RF component in the source current. If the f_(LO) signal is to be used by other components, such as a PLL (Phase Locked Loop), the circuit should not be heavily loaded, and should be buffered by use of signal followers or other known techniques to isolate the circuit from the PLL. If it is desired, a pure oscillator signal can be obtained across nodes n₁₄ and n₁₅. This signal can be provided to other circuits in addition to the use described below.

The role of FN₂ in circuit 30 is now considered. FN₂ is complimentary to FN₁ to integrate the mixer functionality. FN₂ selectively passes the desired mixer output components, f_(LO)−f_(RF) or f_(LO)+f_(RF), to the differential output between f and f′. Additionally, FN₂ blocks the oscillation of the input components, at the desired oscillator frequency f_(LO), from transmission by the differential output. In this manner FN₂ allows device 30 to provide mixer functionality integral with oscillator functionality in a single circuit.

Advantageously, in device 30, the same DC current, I_(dc), provides a bias for both the mixer and oscillator functions, which provides power, cost, and component area savings. Furthermore, the proximity between oscillator function and mixer function achieved via integration of these functions reduces leakage of the local oscillator signal to other circuits.

The concepts taught by example in FIG. 3 are adapted for use in a double balanced circuit 40 in FIG. 4. In this embodiment, the device 40 consists of two differential pairs, the pair formed by Q₇ and Q₈, and the pair formed by Q₉ and Q₁₀. The emitters of Q₇ and Q₈, e₇ and e₈ respectively, are connected to common emitter n₂₁, which is connected to current source I₄. The emitters of Q₉ and Q₁₀, e₉ and e₁₀ respectively, are connected to common emitter n₂₃, which is connected to current source I₅. The current source I₄ for the Q₇ and Q₈ pair contains components I_(dc)+I_(RF), while the current source I₅ for the Q₉ and Q₁₀ pair contains components I_(dc)−I_(RF).

FN₃, a filter network analogous to FN₁ of device 30, connects the collectors (c₇, c₈, c₉, and c₁₀) in pairs so as to generate a frequency selective negative resistance, analogous to the one described above in reference to FIG. 3. This frequency selective negative resistance is used in the oscillator function of device 40. Collectors c₇, c₈, c₉ and c₁₀ are connected to nodes n₂₈, n₂₆, n₂₇ and n₂₉ of FN₃ respectively. Bases b₇ and b₁₀ are connected to the common connection point n₂₅ whereas bases b₈ and b₉ are connected to the common connection point n₂₄, both n₂₅ and n₂₄ are connected to FN₃.

FN₃ preferably connects nodes n₂₈ and n₂₉ with node n₂₄ thereby connecting collectors c₇ and c₁₀ with bases b₈ and b₉ respectively, as well as preferably connecting nodes n₂₆ and n₂₇ with node n₂₅ thereby connecting collectors c₈ and c₀ with bases b₇ and b₁₀ respectively. In so doing, FN₃ provides two negative resistance cells in parallel. The first negative resistance cell is provided by connecting collectors c₈ and c₇ of transistors Q₈ and Q₇ to bases b₇ and b₈ respectively. This connection provides a first cell impedance between bases b₇ and b₈. The second negative resistance cell is provided by connecting collectors c₉ and c₁₀ of transistors Q₉ and Q₁₀ to bases b₁₀ and b₉ respectively. This second connection creates a second cell impedance between bases b₉ and b₁₀. The two negative resistance cells are connected in parallel because bases b₇ and b₈ of the first negative resistance cell are connected to bases b₁₀ and b₉ respectively of the second negative resistance cell.

A connection between any of n₂₈ and n₂₆, n₂₉ and n₂₇, n₂₄ and n₂₅, and various nodes internal to the FN₃ network, that has an impedance with a real component larger than the effective negative resistance provided by the parallel arrangement of the negative resistance cells causes circuit 40 to oscillate. As before the frequency of the oscillation is determined by the impedance of the connection. By selecting the impedance of the connection appropriately, circuit 40 provides an oscillating signal with the desired frequency. FN₃ is connected to the rest of circuit 40 via nodes n₂₄, n₂₅, n₂₆, n₂₇, n₂₈ and n₂₉. The value of the negative resistance created by FN₃ is dependant upon the source current. In device 40, FN₃ is driven by I₄ and I₅, whereas circuit 30 is driven by only I₃. I₄=I_(dc)+I_(RF), while I₅=I_(dc)−I_(RF), so the net current provided, I₄+I₅, is (I_(dc)+I_(RF))+(I_(dc)−I_(RF)) or 2I_(dc). Because the negative resistance is dependant upon the source current, the overall negative resistance provided by the parallel negative resistance cells remains substantially constant over variations in I_(RF). This is an advance over the novel device 30 as illustrated in FIG. 3. Knowing that the impedance of the parallel negative resistance cells is substantially constant, all that must be done to provide oscillator functionality to circuit 40 is to have FN₃ provide an impedance that has a real component greater than the real component of the parallel negative resistance cells.

Advantageously, circuit 40 retains features of a traditional oscillator function as the oscillator output can be taken between bases b₇ and b₈, bases b₉ and b₁₀, or nodes n₂₄ and n₂₅.

FN₄, a filter network analogous to FN₂ of FIG. 3, is used to selectively pass the desired output frequencies to the mixer output between g and g′, while rejecting components at the desired oscillator frequency. FN₄ is connected to circuit 40 via nodes n₃₀, n₃₁, n₃₂, n₃₃, n₃₄, and n₃₅ which are connected to collectors c₇, c₈, c₉ and c₁₀, and mixer outputs g and g′, respectively.

Advantageously, the circuit 40 retains features of a traditional double balanced mixer function, with the mixer output available between nodes g and g′. With a double balanced topology such as that shown in FIG. 4, FN₄ can be designed such that the components at the LO frequency cancel, thereby rejecting the component at the LO frequency, to facilitate selectively passing the desired output components, as will be described in greater detail below in reference to FIG. 6.

FIG. 5 shows an exemplary HPF (High Pass Filter) 50 a suitable for use as a filter network in a frequency down conversion application of the device 40 as illustrated in FIG. 4. Capacitors X₁, and X₂ are connected in series and are arranged to define node n₂₈ connected to the first capacitor X₁, node n₂₄ common to capacitors X₁ and X₂ and node n₂₉ connected to capacitor X₂. Capacitors X₃, and X₄ are connected in an analogous fashion defining node n₂₆ connected to capacitor X₃, node n₂₅ common to capacitors X₃ and X₄, and node n₂₇ connected to capacitor X₄. Variable capacitor X₅ and inductor L₁ are connected in parallel between nodes n₂₅ and n₂₄.

Capacitors X₁, X₂, X₃ and X₄, when connected as described herein and depicted in FIG. 5, provide cross coupling to generate a negative resistance necessary for oscillator functionality in device 40. The capacitive coupling creates a high pass network and ensures that the generated negative resistance is seen only at high frequencies, which is desirable for frequency down-conversion applications. The combination of X₅ and L₁ form an exemplary tank circuit that can be used to generate sufficient real impedance to support oscillation. Additionally, the variable nature of X₅ provides means for tuning the oscillator frequency.

FIG. 6 shows an exemplary LPF (Low Pass Filter) 60 a suitable for use as a filter network in a frequency down conversion application of the circuit 40 as illustrated in FIG. 4. Inductors L₂ and L₄ are connected in series and are arranged to define node n₃₀ connected to inductor L₂, node n₃₄ common to inductors L₂ and L₄ and node n₃₂ connected to inductor L₄. Inductors L₃, and L₅ are connected in an analogous fashion defining node n₃₁ connected to inductor L₃, node n₃₅ common to inductors L₃ and L₅, and node n₃₃ connected to inductor L₅.

At low frequencies LPF 60 operates to connect c₇ to c₉ and c₈ to c₁₀ as typically found in a double balanced mixer. These connections allow LPF 60 to cancel the RF and LO frequency components at the output, while selectively passing the RF−LO frequency component.

Referring to FIG. 7, an input stage circuit 70 is illustrated. Input stage circuit 70 is used, in one embodiment, to provide input currents for the double balanced device 40 of FIG. 4. A differential pair of transistors Q₁₁ and Q₁₂ is shown. An RF signal source S₂ drives a radio frequency signal I₇∝I_(RF) between bases b₁₁, and b₁₂, with output at nodes h and h′.

To reduce the noise contributions of the input differential pair biasing for Q₁₁ and Q₁₂ is provided in this embodiment. The biasing is such that at low frequencies it presents low impedance, in order to minimize noise appearing at b₁₁ and b₁₂. This noise, if unimpeded, modulates the oscillator and appears as phase noise at the oscillating nodes (bases b₇ and b₈, bases b₉ and b₁₀, or other nodes internal to FN3).

Inductors L₆ and L₇ are connected in series between bases b₁₁ and b₁₂ to provide at low frequencies, typically from DC to 5 or 10 MHz, low impedance which reduces phase noise. At high frequencies, typically near RF, L₆ and L₇ provide high impedance to avoid shunting the desired RF signal away from the bases. A bias voltage V_(bias) is provided between inductors L₆ and L₇ to satisfy the biasing requirements of both Q₁₁ and Q₁₂.

If linearity requirements are such that degenerative impedance is suggested, inductors L₈ and L₉ connected in series between emitters e₁₁ and e₁₂ are used for the same reasons as L₆ and L₇ above. However, if degenerative impedance is not suggested, then inductors L₈ and L₉ can be replaced by short circuits. A DC source, I₈=2*I_(dc), is connected between inductors L₈ and L₉.

The two output signals, I₉=I_(dc)+I_(RF) and I₁₀=I_(dc)−I_(RF), are provided by collectors c₁₁ and c₁₂ of transistors Q₁₁ and Q₁₂, at nodes h and h′ respectively. Circuit 70 is therefore used in a presently preferred embodiment to provide source I₄ and I₅ for device 40 by connecting nodes h and h′ of input stage circuit 70 to nodes n₂₁ and n₂₃ of device 40, respectively.

Although not expressly shown in the drawings, any type of transistor can be used, including but not limited to Field Effect Transistors (FET's), GaAs devices, PHemt, and the like. Furthermore, although NPN transistors are used in the drawings, it would be obvious to a person skilled in the art to use complementary devices and invert the structure illustrated, or to use both non-complementary and complementary devices. Further still, current sources can be realized in different ways such as by using resistors and inductors and substitution of one current source for another will be obvious to a person skilled in the art. Also, although the drawings illustrate using a HPF for FN₃ and a LPF for FN₄ in a frequency down conversion application, it would be obvious to a person skilled in the art to invert their roles and use a LPF for FN₃ and a HPF for FN₄ in a frequency up conversion application. It Would be obvious as well to a person skilled in the art to use voltage signals instead of or in conjunction with the current signals illustrated. Other types of filter structures can be used, and the use of alternate filter structures will also be obvious to a person skilled in the art. Other types of filters can lead to other applications, which are also considered to be within the scope of the invention.

The above-described embodiments of the present invention are intended to be examples only. Those of skill in the art may effect alterations, modifications and variations to the particular embodiments without departing from the scope of the invention, which is defined solely by the claims appended hereto. 

1. Circuitry for receiving a time varying input signal and for generating an oscillating output signal and a mixed output signal, comprising: a differential transistor pair for receiving the time varying input signal and for generating a differential pair output signal having a time varying input signal component and other signal components; a first filter network, coupled to the differential pair at a pair of nodes, for receiving the time varying input signal component and for selectively providing the oscillating output signal through a negative resistance generated between the pair of nodes; and a second filter network, coupled to the pair of nodes, for receiving the oscillating output signal, and also coupled to the differential pair for receiving the other signal components and for generating and selectively passing the mixed output signal.
 2. The circuitry of claim 1, wherein the time varying input signal has time varying and constant components.
 3. The circuitry of claim 1, wherein the magnitude of the negative resistance is proportional to the magnitude and frequency of the time varying input signal.
 4. The circuitry of claim 1, wherein the first filter network generates the negative resistance across nodes connected to the collectors of the differential pair of transistors.
 5. The circuitry of claim 1, wherein the second filter network includes means for generating the mixed output signal by translation of the oscillating output signal by the frequency of the time varying signal.
 6. The circuitry of claim 5, wherein the mixed output signal has a frequency equal to the frequency of the oscillating output signal plus the frequency of the time varying input signal.
 7. The circuitry of claim 5, wherein the mixed output signal has a frequency equal to the frequency of the oscillating output signal minus the frequency of the time varying input signal.
 8. The circuitry of claim 1, further comprising: a second differential transistor pair for receiving a second time varying input signal, the second differential transistor pair being coupled to the first and second filter networks for providing the second time varying input signal; wherein the first filter network creates a negative resistance across two pairs of nodes in parallel with each other, and wherein the second filter network cancels output signals at the frequency of the oscillating output signal.
 9. The circuitry of claim 8, wherein the first and second time varying signals have time varying and constant components.
 10. The circuitry of claim 8, wherein the first and second time varying signals are out of phase with each other.
 11. The circuitry of claim 8, wherein the overall negative resistance of the parallel negative resistances is substantially constant.
 12. The circuitry of claim 1, wherein the first filter network is a high pass filter.
 13. The circuitry of claim 12, wherein the high pass filter is tuneable.
 14. The circuitry of claim 1, wherein the second filter network is a low pass filter.
 15. The circuitry of claim 1 wherein the first filter network is a low pass filter.
 16. The circuitry of claim 15, wherein the low pass filter is tuneable.
 17. Apparatus, comprising: means for receiving a time varying input signal and for generating an output signal having a time varying input signal component and other signal components; means, coupled to the means for receiving a time varying input signal at a pair of nodes, for receiving the time varying input signal component and for selectively providing an oscillating output signal through a negative resistance generated between the pair of nodes; and means, coupled to the pair of nodes, for receiving the oscillating output signal, and also coupled to the means for receiving a time varying input signal, for receiving the other signal components and for generating and selectively passing a mixed output signal.
 18. A mixillator circuit, comprising: a pair of transistors each having a first, a second and a third terminal, wherein the first terminals of the pair of transistors are coupled together and connected to a time varying input signal; a first filter network coupled to the second and third terminals of the pair of transistors, for receiving the time varying input signal and for generating an oscillator output signal; and a second filter network, coupled to the third terminals of the pair of transistors, for receiving the oscillator output signal and for generating a mixer output signal by translating the oscillator output signal.
 19. The mixillator circuit of claim 18, wherein the pair of transistors are bipolar junction transistors, and wherein the first, second and third terminals of the pair of transistors are respectively the emitter, base and collector terminals of the bipolar junction transistors.
 20. The mixillator circuit of claim 18, wherein the first filter network provides a negative resistance between the third terminals of the pair of transistors.
 21. The mixillator circuit of claim 18, further comprising a current source coupled to the first terminals of the pair of transistors for providing the time varying input signal.
 22. The mixillator circuit of claim 21, the time varying input signal includes DC current components and time varying current components.
 23. The mixillator circuit of claim 20, wherein the first filter network provides a negative resistance at a desired oscillator frequency, Fose.
 24. The mixillator circuit of claim 23, the first filter network does not provide a negative resistance at a desired mixer frequency, Fmixer, wherein Fmixer is at a distinct frequency from Fose.
 25. The mixillator circuit of claim 18, wherein the second filter network blocks the oscillator output signal.
 26. The mixillator circuit of claim 18, wherein the second filter network generates the mixer output signal by translating the oscillator output signal by a positive amount equal to the frequency of the time varying input signal.
 27. The mixillator circuit of claim 18, wherein the second filter network generates the mixer output signal by translating the oscillator output signal by a negative amount equal to the frequency of the time varying input signal. 